language: en

Low-Energy Asynchronous Memory Design

Jose A. Tierno Alain J. Martin
California Institute of Technology
Pasadena, CA 91125

Abstract We introduce the concept of energy per operation as a measure of performance of an asynchronous circuit. We show how to model energy consumption based on the high-level language specification. This model is independent of voltage and timing considerations. We apply this model to memory design. We show first how to dimension a memory array, and how to break up this memory array into smaller arrays to minimize the energy per access. We then show how to use cache memory and pre-fetch mechanisms to further reduce energy per access.

Keywords: Low-energy, low-power, asynchronous design, memory design.

1 Introduction