language: en

Gate Load Delay Computation Using Analytical Models

Andrew B. Kahng Sudhakar Muddu
UCLA Computer Science Department Silicon Graphics, Inc.
Los Angeles, CA 90095-1596 USA Mountain View, CA 94039 USA
abk@cs.ucla.edu muddu@mti.sgi.com

Abstract With submicron technologies, gate delays are dominated by gate load delays rather than intrinsic gate delays. While the common approach for computing gate load delay (or total gate delay) is through delay tables (or k-factor equations), there are important methodology problems associated with the delay table approach. In this paper, we propose a gate driver model with a Thevenin equivalent circuit consisting of a ramp voltage source whose slew time is obtained from the gate slew tables, and a driver resistance in series with the gate load. We then develop analytical gate delay formulas using this Thevenin driver model and modeling the load with various gate load models under both rising and falling ramp input.

1 Introduction