language: en

Efficient Gate Delay Modeling for Large Interconnect Loads

Andrew B. Kahng and Sudhakar Muddu
UCLA Computer Science Department,
Los Angeles, CA 90095-1596 USA
abk@cs.ucla.edu, sudhakar@cs.ucla.edu

Abstract With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant impact on logic gate delay. In this paper, we propose a new P model for distributed RC and RLC interconnects to estimate the driving point admittance at the output of a CMOS gate. Using this model we are able to compute the gate delay efficiently, within 25% of SPICE-computed delays. Our parameters depend only on total interconnect tree resistance and capacitance at the output of the gate. Previous effective load capacitance methods [7, 9], applicable only for distributed RC interconnects, are based on P model parameters obtained via a recursive admittance moment computation. Our model should be useful for iterative optimization of performance-driven routing or for estimation of gate delay and rise times in high-level synthesis.

Keywords: gate delay, reduced-order models, driving point admittance, effective capacitance, interconnect modeling

1 Introduction